The present invention relates to a method for manufacturing a ceramic capacitor embedded in a wiring substrate.
In recent years, a semiconductor integrated circuit device (IC chip) used as a microprocessor etc. for a computer has increasingly increased in speed and performance, and the number of terminals has increased also a terminal pitch has narrowed with increase in these speed and performance. Normally, a number of terminals are densely arranged in an array pattern on a bottom surface of the IC chip, and such terminal group are connected with terminal group on a motherboard side through flip-chip mounting. Here, there is a large difference in terminal pitch between the terminal group on the IC chip side and the terminal group on the motherboard side, it is therefore difficult to directly mount and connect the IC chip on and with the motherboard. For this problem, such a manner that a package in which the IC chip is mounted on an IC chip mounting wiring substrate is prepared and this package is mounted on the motherboard, is normally employed. Regarding the IC chip mounting wiring substrate that is a component of this kind of package, it has been proposed that a capacitor be provided in the IC chip mounting wiring substrate for reducing switching noises of the IC chip and for stabilizing power supply voltage. As an example, Patent Document 1 (Japanese Patent Provisional Publication No. 2005-39243 (JP2005-39243)) discloses a wiring substrate, e.g. in FIG. 4. This wiring substrate has a core substrate, which is made of polymeric material, and build-up layers. More specifically, a ceramic capacitor is embedded in the core substrate, and the build-up layers are formed on a front surface and a back surface of the core substrate, then the wiring substrate having such configuration is provided.
In the following, an example of a manufacturing method of the related art wiring substrate will be explained with reference to FIGS. 31 and 32.    First, a core substrate 204 made of the polymeric material is provided. The core substrate 204 has an installation opening part 203 that opens on both sides of a core main surface 201 and a core back surface 202 (see FIG. 31). In addition, a ceramic capacitor 208 is provided. The ceramic capacitor 208 has a pair of capacitor main surfaces (first and second capacitor main surfaces) 205 and four capacitor side surfaces 206, and a plurality of projecting surface layer electrodes 207 are formed on the both capacitor main surfaces 205.    Second, a taping process in which an adhesive tape 209 is taped on the core back surface 202 side is performed, then the opening of the installation opening part 203 on the core back surface 202 side is previously sealed. Subsequently, an installation process in which the ceramic capacitor 208 is installed in the installation opening part 203 is performed, then the capacitor main surface 205 is stuck to an adhesive surface of the adhesive tape 209 for a temporary fixation (see FIG. 31).
Next, a gap between an inner surface of the installation opening part 203 and the capacitor side surface 206 is filled with a filling material 210 that is made of resin insulation material (see FIG. 32). Here, the filling material 210 has the function of fixing the ceramic capacitor 208 to the core substrate 204 with the filling material 210 being contiguous with an outer surface of the ceramic capacitor 208. Afterwards, a resin interlayer insulation layer that is made of mainly polymeric material and a conductor layer are alternately formed on the core main surface 201 also on the core back surface 202 of the core substrate 204, then the build-up layers are formed. Through these processes, a desired wiring substrate is obtained.
In such wiring substrate, however, when a stress is applied to the filling material 210 due to heat etc. generated during operation of the IC chip, the stress concentrates at a corner portion 200 (a boundary portion between the first capacitor main surface 205 and the capacitor side surface 206) of the ceramic capacitor 208, and there is a possibility that a crack will appear in the filling material 210. This crack could become a factor that breaks the build-up layer that is contiguous to the filling material 210. Therefore, for instance, in Patent Document 2 (Japanese Patent Provisional Publication No. 2004-172305 (JP2004-172305)), by polishing the ceramic capacitor 208 through a barrel finishing process for a certain time, a curved chamfer portion (not shown) is formed at the boundary portion between the first capacitor main surface 205 and the capacitor side surface 206. With this technique, since the stress concentration to the corner portion 200 of the ceramic capacitor 208 relaxes by the chamfer portion, it is conceivable that the occurrence of the crack in the filling material 210 could be prevented.